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该全加器程序由以下三个子程序构成

1）“f_adder”全加器程序

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY f_adder IS	PORT (ain,bin,cin:IN STD_LOGIC;		  cout,sum:OUT STD_LOGIC);END ENTITY f_adder;ARCHITECTURE fd1 OF f_adder IS	COMPONENT h_adder		PORT (a,b:IN STD_LOGIC;			  co,so:OUT STD_LOGIC);	END COMPONENT;	COMPONENT or2a		PORT(a,b:IN STD_LOGIC;			 c: OUT STD_LOGIC);	END COMPONENT;SIGNAL d,e,f : STD_LOGIC;				BEGIN	u1: h_adder PORT MAP(a=>ain,b=>bin,co=>d,so=>e);	u2: h_adder PORT MAP(a=>e,b=>cin,co=>f,so=>sum);	u3: or2a PORT MAP(a=>d,b=>f,c=>cout);END ARCHITECTURE fd1;

2）“h_adder半加器程序”

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder IS	PORT (a,b:IN STD_LOGIC;		  co,so:OUT STD_LOGIC);END ENTITY h_adder;ARCHITECTURE fh1 OF h_adder ISBEGIN	so<=NOT(a XOR (NOT b));	co<=a AND B;END ARCHITECTURE fh1;

3）“or2a 或门程序”

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY or2a IS	PORT(a,b:IN STD_LOGIC;		 c: OUT STD_LOGIC);END ENTITY or2a;ARCHITECTURE one OF or2a IS	BEGIN 		c<=a OR b;END ARCHITECTURE one;

程序仿真效果如下图